View ETC5067_97509.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

ETC5064/64-X ETC5067/67-X
SERIAL INTERFACE CODEC/FILTER WITH RECEIVE POWER AMPLIFIER
.COMPLETE
..A.MEETSOREXCEEDSALLD3/ .5VOPERATI .LOWOPERATI .POWER.AUTOMATI .TTLORCMOSCOMPATI .MAXI .0CTO70 .-40CTO85COPERATI
CODEC AND FILTERING SYSTEM INCLUDING : - Transmit high-pass and low-pass filtering. - Receive low-pass filter with sin x/x correction. - Active RC noise filter. - -law or A-law compatible CODER and DECODER. - Internal precision voltage reference. - Serial I/O interface. - Internal auto-zero circuitry. - Receive push-pull power amplifiers. LAW ETC5064 LAW ETC5067 D4 AND CCITT SPECIFICATIONS. ON. NG POWER-TYPICALLY 70 mW DOWN STANDBY MODE-TYPICALLY 3 mW C POWER DOWN BLE DIGITAL INTERFACES MIZES LINE INTERFACE CARD CIRCUIT DENSITY C OPERATION: ETC5064/67 ON: ETC5064-X/67-X
DIP20 (Plastic) N ORDERING NUMBERS: ETC5064N ETC5064N-X ETC5067N ETC5067N-X
PL CC20 FN ORDERING NUMBERS: ETC5064FN ETC5064FN-X ETC5067FN ETC5067FN-X
DESCRIPTION The ETC5064 (-law), ETC5067 (A-law) are monolithic PCM CODEC/FILTERS utilizing the A/D and D/A conversion architectureshown in the Block Diagrams and a serial PCM interface. The devices are fabricated using double-poly CMOS process. Similar to the ETC505X family, these devices feature an additional Receive Power Amplifier to provide push-pull balanced output drive capability. The receive gain can be adjusted by means of two external resistors for an output level of up to 6.6 V across a balanced 600 load. Also included is an Analog Loopback switch and TSX output.
SO 20 D ORDERING NUMBERS: ETC5064D ETC5064D-X ETC5067D ETC5067D-X
November 1994
1/18
ETC5064 - ETC5064-X - ETC5067 - ETC5067-X
PIN CONNECTIONS (Top views)
DIP20 & SO20 PLCC20
BLOCK DIAGRAM (ETC5064 - ETC5064-X - ETC5067 - ETC5067-X)
2/18
ETC5064 - ETC5064-X - ETC5067 - ETC5067-X
PIN DESCRIPTION
Name VPO
+
Pi n Type (*) O GND O I O S I I I
N 1 2 3 4 5 6 7 8 9
Description The Non-inverting Output of the Receive Power Amplifier Analog Ground. All signals are referenced to this pin. The Inverting Output of the Receive Power Amplifier Inverting Input to the Receive Power Amplifier. Also powers down both amplifiers when connected to VBB. Analog Output of the Receive Filter. Positive Power Supply Pin. VCC = +5V 5% Receive Frame Sync Pulse which enable BCLKR to shift PCM data into D R. FSR is an 8KHz pulse train. See figures 1 and 2 for timing details. Receive Data Input. PCM data is shifted into DR following the FSR leading edge The bit Clock which shifts data into DR after the FSR leading edge. May vary from 64KHz to 2.048MHz. Alternatively, may be a logic input which selects either 1.536MHz/1.544MHz or 2.048MHz for master clock in synchronous mode and BCLKX is used for both transmit and receive directions (see table 1). This input has an internal pull-up. Receive Master Clock. Must be 1.536MHz, 1.544MHz or 2.048MHz. May be asynchronous with MCLKX, but should be synchronous with MCLKX for best performance. When MCLKR is connected continuously low, MCLKX is selected for all internal timing. When MCLKR is connected continuously high, the device is powered down. Transmit Master Clock. Must be 1.536MHz, 1.544MHz or 2.048MHz. May be asynchronous with MCLKR. The bit clock which shifts out the PCM data on D X. May vary from 64KHz to 2.048MHz, but must be synchronous with MCLKX. The TRI-STAT E(R)PCM data output which is enabled by FSX. Transmit frame sync pulse input which enables BCLKX to shift out the PCM data on DX. FSX is an 8KHz pulse train. See figures 1 and 2 for timing details. Open drain output which pulses low during the encoder time slot. Must to be grounded if not used. Analog Loopback Control Input. Must be set to logic '0' for normal operation. When pulled to logic '1', the transmit filter input is disconnected from the output of the transmit preamplifier and connected to the VPO+ output of the receive power amplifier. Analog output of the transmit input amplifier. Used to set gain externally. Inverting input of the transmit input amplifier. Non-inverting input of the transmit input amplifier. Negative Power Supply Pin. VBB = -5V 5%
GNDA VPO VPI VFRO VCC FSR DR BCLKR/CLKSEL
-
MCKLR/PDN
I
10
MCLKX BCLKX DX FSX
I I O I
11 12 13 14
TSX ANLB
O I
15 16
GSX VFXI VFXI VBB
+
O I I S
17 18 19 20
(*) I: Input, O: Output, S: Power Supply. TRI-STATE(R) is a trademark of National Semiconductor Corp.
3/18
ETC5064 - ETC5064-X - ETC5067 - ETC5067-X
FUNCTIONAL DESCRIPTION POWER-UP When power is first applied, power-on reset circuitry initializes the device and places it into the powerdown mode. All non-essential circuits are deactivated and the DX and VFRO outputs are put in high impedancestates. To power-upthe device,a logical low level or clock must be applied to the MCLKR/PDN pin and FSX and/or FSR pulses must be present. Thus 2 power-down control modes are available. The first is to pull the MCLKR/PDN pin high; the alternative is to hold both FSX and FSR inputs continuously low. The device will power-down approximately 2 ms after the last FSX pulse. The TRI-STATE PCM data output, DX, will remain in the high impedance state until the second FSX pulse. SYNCHRONOUS OPERATION For synchronous operation, the same master clock and bit clock should be used for both the transmit and receive directions. In this mode, a clock must be applied to MCLKX and the MCLKR/PDN pin can be used as a power-down control. A low level on MCLKR/PDN powers up the device and a high level powers down the device. In either case, MCLKX will be selected as the master clock for both the transmit and receive circuits. A bit clock must also be applied to BCLKX and the BCLR/CLKSELcan be used to select the proper internal divider for a master clock of 1.536 MHz, 1.544 MHz or 2.048 MHz. For 1.544 MHz operation, the device automatically compensates for the 193 rd clock pulse each frame. With a fixed level on the BCLKR/CKSEL pin, BCLKX will be selected as the bit clock for both the transmit and receive directions. Table 1 indicates the frequencies of operation which can be selected, depending on the state of BCLKR/CLKSEL. In this synchronous mode, the bit clock, BCLKX, may be from 64 kHz to 2.048 MHz, but must be synchronouswith MCLKX. Table 1: Selection of Master Clock Frequencies.
Master Clock Frequency Selected ETC5067 ETC5067-X 2.048MHz 1.536MHz or 1.544MHz 2.048MHz ETC5064 ETC5064-X 1.536MHz or 1.544MHz 2.048MHz 1.536MHz or 1.544MHz
Each FSX pulse begins the encoding cycle and the PCM data from the previous encode cycle is shift out of the enabled DX output on the positive edge of BCLKX. After 8 bit clock periods, the TRISTATE DX output is returned to a high impedance state. With an FSR pulse, PCM data is latched via the DR input on the negativeedge of BCLKX (or on BCKLR if running). FSX and FSR must be synchronous with MCLKX/R. ASYNCHRONOUS OPERATION For asynchronous operation, separate transmit and receive clocks may be applied. MCLKX and MCLKR must be 2.048 MHz for the ETC5067 or 1.536 MHz, 1.544 MHz for the ETC5064, and need not be synchronous. For best transmission performance, however, MCLKR should be synchronouswith MCLKX, which is easily achieved by applyingonly static logic levels to theMCLKR/PDN pin. This will automatically connectMCLKX toall internal MCLKR functions(see pin description). For 1.544 MHz operation, the device automatically compensates for the 193rd clock pulse each frame. FSX starts each encoding cycle and must be synchronous with MCLKX and BCLKX. FSR starts each decoding cycle and must be synchronous with BCLKR. BCLKR must be a clock, the logic levels shown in Table 1 are not valid in asynchronous mode. BCLKX and BCLKR may operate from 64kHz to 2.048 MHz. SHORT FRAME SYNC OPERATION The device can utilize either a short frame sync pulse or a long frame sync pulse.Upon power initialization, the device assumes a short frame mode. In this mode, both frame sync pulses. FSX and FSR, must be one bit clock period long, with timing relationships specified in figure 2. With FSX high during a falling edge of BCLKR, the next rising edge of BCLKX enables the DX TRI-STATE output buffer, which will output the sign bit. The following sevenrising edges clock out the remaining seven bits, and the next falling edge disables the DX output. With FSR high during a falling edge of BCLKR (BCLKX in synchronous mode), the next falling edge of BCLKR latches in the sign bit. The following seven falling edges latch in the seven remaining bits. Both devices may utilize the short frame sync pulse in synchronous or asynchronous operating mode. LONG FRAME SYNC OPERATION To use the long frame mode, both the frame sync pulses, FSX and FSR, must be three or more bit clock periods long, with timing relationships specified in figure 3. Based on the transmit frame sync FSX, the device will sense whether short or long frame sync
BCLKR/CLKSEL
Clocked 0 1 (or open circuit)
4/18
ETC5064 - ETC5064-X - ETC5067 - ETC5067-X
pulses are being used. For 64 kHz operation, the frame sync pulses must be kept low for a minimum of 160 ns (see Fig 1). The DX TRI-STATE output buffer is enabled with the rising edge of FSX or the rising edge of BCLKX, whichever comes later, and the first bit clocked out is the sign bit. The following seven BCLKX rising edges clock out the remaining seven bits. The DX output is disabled by the falling BCLKX edge following the eighth rising edge, or by FSX going low, whichever comes later. A rising edge on the receive frame sync pulse, FSR, will cause the PCM data at DR to be latched in on the next eight falling edges of BCLKR (BCLKx in synchronous mode). Both devices may utilize the long frame sync pulse in synchronous or asynchronous mode. TRANSMIT SECTION The transmit section input is an operational amplifier with provision for gain adjustmentusing two external resistors, see figure 4. The low noiseand wide bandwidth allow gains in excess of 20 dB across the audio passband to be realized. The op amp drives a unity gain filter consisting of RC active pre-filter, followed by an eighth order switched-capacitor bandpass filter directly drives the encoder sampleand-hold circuit. The A/D is of companding type according to A-law (ETC5067 and ETC5067-X) or law (ETC5064 and ETC5064-X) coding conventions. A precision voltage reference is trimmed in manufacturing to provide an input over load (tMAX) of nominally 2.5V peak (see table of Transmission Characteristics). The FSX frame sync pulse controls the sampling of the filer output,and then the successive-approximationencodingcycle begins.The8-bit code is then loaded into a buffer and shifted out throughDX at the next FSX pulse. the total encoding delay will be approximately 165s (due to the transmit filter) plus 125s (due to encoding delay), which totals 290s. Any offset voltage due to the filters or comparator is cancelled by sign bit integration. ABSOLUTE MAXIMUM RATINGS
Symbol VCC VBB VIN, VOUT Toper Tstg VCC to GNDA VBB to GNDA Voltage at any Analog Input or Output Voltage at any Digital Input or Output Operating Temperature Range: ETC5064/67 ETC5064-X/67-X Storage Temperature Range Lead Temperature (soldering, 10 seconds) Parameter Valu e 7 -7 VCC +0.3 to VBB -0.3 VCC +0.3 to GNDA -0.3 -25 to +125 -40 to +125 -65 to +150 300 Un it V V V V C C C C
RECEIVE SECTION The receive section consist of an expanding DAC which drives a fifth order switched-capacitor low pass filter clocked at 256kHz. The decoder is A-law (ETC5067 and ETC5067-X) or -law (ETC5064 and ETC5064-X) and the 5 th order low pass filter corrects for the sin x/x attenuation due to the 8kHz sample and hold. The filter is then followed by a 2 nd order RC active post-filter and power amplifier capable of driving a 600 load to a level of 7.2dBm. The receive section is unity-gain. Upon the occurence of FSR, the data at the DR input is clocked in on the falling edge of the next eight BCLKR (BCKLX) periods.At the endofthe decoder time slot, the decoding cycle begins, and 10s later the decoder DAC outputis updated.The total decoder delay is about10s (decoder up-date) plus 110s (filter delay) plus 62.5s (1/2 frame), which gives approximately 180s. RECEIVE POWER AMPLIFIERS Two inverting mode power amplifiers are provided for directly driving a matched line interface transformer. The gain of the first power amplifier can be adjusted to boost the 2.5V peak output signal from the receive filter up 3.3V peak into an unbalanced 300 load, or 4.0V into an unbalanced15k load. The second power amplifier is internally connected in unity-gain inverting mode to give 6dB of signal gain for balanced loads. Maximum power transfer to a 600 subscriber line termination is obtained by differientially driving a balanced transformer with a : 1 turns ratio, as shown in figure 4. A total peak 2 power of 15.6dBm can be delivered to the load plus termination. Both power amplifier can be powered down independentlyfrom the PDN input by connecting the VPI input to VBB saving approximately 12 mW of power.
5/18
ETC5064 - ETC5064-X - ETC5067 - ETC5067-X
ELECTRICAL OPERATING CHARACTERISTICS VCC = 5.0V 5%, VBB = -5V 5%, GNDA = 0V, TA = 0C to70C (ETC5064-X/67-X: TA = -40C to 85), unless otherwise noted; typical characteristics specified at VCC = 5.0V, VBB =-5.0V, TA = 25C; all signals are referenced to GNDA. DIGITAL INTERFACE (All devices)
Symbol VIL VIH VOL Input Low Voltage Input High Voltage Output Low Voltage IL = 3.2 mA IL = 3.2 mA, Open Drain Output High Voltage IH = 3.2 mA Input Low Current (GNDA VIN VIL )all digital inputs Except BCLKR Input High Current (VIH VIN VCC) Except ANLB Output Current in High Impedance State (TRI-STAT E) (GNDA VO VCC) DX DX TSX DX 2.4 - 10 - 10 - 10 10 10 10 2.2 0.4 0.4 Parameter Min. Typ. Max. 0.6 Unit V V V V V A A A
VOH IIL IIH IOZ
ANALOG INTERFACE WITH TRANSMIT INPUT AMPLIFIER (all devices)
Symbol IIXA R IXA R OXA R LXA C LXA VOXA AVXA FUXA VOSXA VCMXA CMRRXA PSRRXA Input Leakage Current (- 2.5 V V + 2.5 V) Input Resistance (- 2.5 V V + 2.5 V) Output Resistance (closed loop, unity gain) Load Resistance Load Capacitance Output Dynamic Range (RL 10 k) Voltage Gain (VFXI to GSX) Unity Gain Bandwidth Offset Voltage Common-mode Voltage Common-mode Rejection Ratio Power Supply Rejection Ratio
+
Parameter VFxI or VFxI VFXI
+ + -
Min. - 200
-
Typ.
Max. 200
Unit nA M
or VFXI
10 1 3 50 - 2.8 5000 1 - 20 - 2.5 60 60 2 20 2.5 +2.8
k pF V V/V MHz mV V dB dB
GSX GSX GSX
10
ANALOG INTERFACE WITH RECEIVE FILTER (all devices)
Symbol R ORF R LRF C LRF VOSRO Output Resistance Load Resistance (VFRO = 2.5 V) Load Capacitance Output DC Offset Voltage - 200 Parameter VFRO 10 25 200 Min. Typ. 1 Max. 3 Unit k pF mV
6/18
ETC5064 - ETC5064-X - ETC5067 - ETC5067-X
ELECTRICAL OPERATING CHARACTERISTICS (Continued) ANALOG INTERFACE WITH POWER AMPLIFIERS (all devices)
Symbol IPI RIPI VIOS ROP FC CLP Parameter Input Leakage Current (- 1.0 V VPI 1.0 V) Input Resistance (- 1.0 VPI 1.0 V) Input Offset Voltage Output Resistance (inverting unity-gain at VPO + or VPO -) Unity-gain Bandwidth, Open Loop (VPO ) Load Capacitance (VPO + or VPO - to GNDA) RL 1500 RL = 600 RL = 300
+ -
Min. - 100 10 - 25
Typ.
Max. 100 25
Unit nA M mV kHz pF
1 400 100 500 1000
GAp
Gain VPO to VPO to GNDA, Level at VPO = 1. 77 Vrms (+ 3 dBmO) Power Supply Rejection of VCC or VBB (VPO- connected to VPI) 0 kHz - 4 kHz 0 kHz - 50 kHz
-
+
-
-1
V/V dB
PSRRp
60 36
POWER DISSIPATION (all devices)
Symbol ICC0 IBB0 ICC1 IBB1 Parameter Power-down Current at ETC6064/67 ETC5064-X/67-X Power-down Current at ETC6064/67 ETC5064-X/67-X Active Current at ETC6064/67 ETC5064-X/67-X Active Current at ETC6064/67 ETC5064-X/67-X Min. Typ. 0.5 0.5 0.05 0.05 7.0 7.0 7.0 7.0 Max. 1.5 0.3 0.4 10.0 12.0 10.0 12.0 Unit mA mA mA mA mA mA mA mA
7/18
ETC5064 - ETC5064-X - ETC5067 - ETC5067-X
All TIMING SPECIFICATIONS
Symbol 1/tPM Parameter Frequency of master clocks MCLKX and MCLKR Depends on the device used and the BCLKR/CLKSEL Pin Width of Master Clock High Width of Master Clock Low Rise Time of Master Clock Fall Time of Master Clock Period of Bit Clock Width of Bit Clock High (VIH = 2.2 V) Width of Bit Clock Low (VIL = 0.6 V) Rise Time of Bit Clock (tPB = 488 ns) Fall Time of Bit Clock (tPB = 488 ns) Set-up time from BCLKX high to MCLKX falling edge. (first bit clock after the leading edge of FSX) Holding Time from Bit Clock Low to the Frame Sync (long frame only) Set-up Time from Frame Sync to Bit Clock (long frame only) Hold Time from 3rd Period of Bit Clock Low to Frame Sync (long frame only) FSX or FSR 100 0 80 100 20 165 MCLKX and MCLKR MCLKX and MCLKR MCLKX and MCLKR MCLKX and MCLK R 485 160 160 50 50 488 160 160 50 50 15.725 Min. Typ. 1.536 2.048 1.544 ns ns ns ns ns ns ns ns ns ns ns ns ns ns Max. Unit MHz
tWMH tWML tRM tFM tPB tWBH tWBL tRB tFB tSBFM tHBF tSFB tHBFI tDZF
Delay Time to valid data from FSX or BCLKX, whichever comes later and delay time from FSX to data output disabled (CL = 0 pF to 150 pF) Delay Time from BCLKX high to data valid (load = 150 pF plus 2 LSTTL loads) Delay Time from BCLKX low to data output disabled Set-up Time from DR valid to BCLKR/X low Hold Time from BCLKR/X low to DR invalid Holding Time from Bit Clock High to Frame Sync (short frame only) Set-up Time from FSX/R to BCLKX/R Low (short frame sync pulse) - Note 1 Hold Time from BCLKX/R Low to FSX/R Low (short frame sync pulse) - Note 1 Delay Time to TSX low (load = 150 pF plus 2 LSTTI loads) Minimum Width of the Frame Sync Pulse (low level) (64 bit/s operating mode)
tDBD tDZC tSDB tHBD tHOLD tSF tHF tXDP tWFL
0 50 50 50 0 80 100
150 165
ns ns ns ns ns ns ns
140 160
ns ns
Note : 1.For short frame sync timing. FS X and FSR must go high while their respective bit clocks are high.
Figure 1 : 64 k bits/s TIMING DIAGRAM. (see next page for complete timing)
8/18
ETC5064 - ETC5064-X - ETC5067 - ETC5067-X
Figure 2 : Short Frame Sync Timing.
9/18
ETC5064 - ETC5064-X - ETC5067 - ETC5067-X
Figure 3 : Long Frame Sync Timing.
10/18
ETC5064 - ETC5064-X - ETC5067 - ETC5067-X
TRANSMISSION CHARACTERISTICS (all devices) TA = 0C to 70C (ETC5064-X/67-X: TA = -40C to 85), VCC = 5V 5%, VBB = - 5V 5%, GNDA = 0V, f = 1.02kHz, VIN = 0dBm0 transmit input amplifier connected forunity-gainnon-inverting.(unless otherwise specified). AMPLITUDE RESPONSE
Symbo l Parameter Absolute Levels - Nominal 0 dBm0 is 4 dBm (600). 0 dBm0 tMAX Max Overload Level 3.14 dBm0 3.17 dBm0 ETC5067 ETC5064 -0.15 Min. T yp. 1.2276 Max. Unit Vrms
2.492 2.501 0.15
VPK dB
GXA GXR
Transmit Gain, Absolute (TA = 25C, VCC = 5V, VBB = -5V) Input at GSX = 0dBm0 at 1020Hz Transmit Gain, Relative to GXA f = 16Hz f = 50Hz f = 60Hz f = 180Hz f = 200Hz f = 300Hz -3000Hz f = 3200Hz (ETC5064-X/67-X) f = 3300Hz f = 3400Hz f = 4000Hz f = 4600Hz and up, measure response from oHz to 4000Hz Absolute Transmit Gain Variation with Temperature TA = 0C to +70C TA = -40C to +85C (ETC5064-X/67-X) Absolute Transmit Gain Variation with Supply Voltage (VCC = 5V 5%, VBB = -5V 5%) Transmit Gain Variation with Level Sinusolidal Test Method Reference Level = -10dBm0 VFXI+ = -40dBm0 to +3dBm0 + VFXI = -50dBm0 to -40dBm0 + VFXI = -55dBm0 to -50dBm0 Receive Gain, Absolute (TA = 25C, VCC = 5V, VBB = -5V) Input = Digital Code Sequence for 0dBm0 Signal at 1020Hz Receive Gain, Relative to GRA f = 0Hz to 3000Hz f = 3200Hz (ETC5064-X/67-X) f = 3300Hz f = 3400Hz f = 4000Hz Absolute Receive Gain Variation with Temeperature TA = 0C to +70C TA = -40C to +85C (ETC5064-X/67-X) Absolute Receive Gain Variation with Supply Voltage (VCC = 5V 5%, VBB = -5V 5%) Receive Gain Variation with Level Sinusoidal Test Method; Reference Input PCM code corresponds to an ideally encoded -10dBm0 signal PCM level = -40dBm0 to +3dBm0 PCM level = -50dBm0 to -40dBm0 PCM level = -55dBm0 to -50dBm0 Receive Filter Output at VFRO R L = 10K
-2.8 -1.8 -0.15 -0.35 -0.35 -0.7
-40 -30 -26 -0.2 -0.1 0.15 0.20 0.05 0 -14 -32 0.1 0.15 0.05
dB
GXAT
dB -0.1 -0.15 -0.05
GXAV GXRL
dB
-0.2 -0.4 -1.2 -0.15
0.2 0.4 1.2 0.15
dB
GRA GRR
dB
-0.15 -0.35 -0.35 -0.7
0.15 0.20 0.05 0 -14 0.1 0.15 0.05
dB
GRAT
-0.1 -0.15 -0.05
dB dB
GRAV GRRL
-0.2 -0.4 -1.2 -2.5
0.2 0.4 1.2 2.5
dB
VRO
V 11/18
ETC5064 - ETC5064-X - ETC5067 - ETC5067-X
TRANSMISSION CHARACTERISTICS (continued). ENVELOPE DELAY DISTORTION WITH FREQUENCY
Symbol DXA DXR Parameter Transmit Delay, Absolute (f = 1600 Hz) Transmit Delay, Relative to DXA f = 500 Hz-600 Hz f = 600 Hz-800 Hz f = 800 Hz-1000 Hz f = 1000 Hz-1600 Hz f = 1600 Hz-2600Hz f = 2600 Hz-2800 Hz f = 2800 Hz-3000 Hz Receive Delay, Absolute (f = 1600 Hz) Receive Delay, Relative to DRA f = 500 Hz-1000 Hz f = 1000 Hz-1600 Hz f = 1600 Hz-2600 Hz f = 2600 Hz-2800 Hz f = 2800 Hz-3000 Hz - 40 - 30 Min. Typ. 290 195 120 50 20 55 80 130 180 - 25 - 20 70 100 145 Max. 315 220 145 75 40 75 105 155 200 Unit s
s
DRA D RR
s
s 90 125 175
NOISE
Symbol NXP Parameter Transmit Noise, P Message (A-LAW, VFXI ETC5064 ETC5064-X Receive Noise, P Message Weighted (A-LAW, PCM Code Equals Positive Zero) Transmit Noise, C Message Weighted (-LAW, VFxI + = 0 V) ETC5064 ETC5064-X
+
Min. = 0 V) Weighted 1)
Typ. - 74 - 74 - 82
Max. - 69 - 67 - 79
Unit dBm0p dBm0p dBm0p
NRP NXC
12 12 8
15 16 11 - 53
dBrnC0 dBrnC0 dBrnC0 dBm0 dBp dBp
N RC NRS PPSRX NPSRX PPSRR
Receive Noise, C Message Weighted (-LAW, PCM Code Equals Alternating Positive and Negative Zero) Noise, Single Frequency + f = 0 kHz to 100 kHz, Loop around Measurement, VFXI = 0 V Positive Power Supply Rejection, Transmit (note 2) VCC = 5.0 VDC + 100 mVrms, f = 0 kHz-50 kHz Negative Power Supply Rejection, Transmit (note 2) VBB = 5.0 VDC + 100 mVrms, f = 0 kHz-50 kHz Positive Power Supply Rejection, Receive (PCM code equals positive zero, VCC = 5.0 VDC + 100 mVrms) f = 0 Hz-4000Hz A LAW LAW f = 4 kHz-25 kHz f = 25 kHz-50 kHz Negative Power Supply Rejection, Receive (PCM code equals positive zero, VBB = - 5.0 VDC + 100 mVrms) f = 0 Hz-4000Hz A LAW LAW f = 4 kHz-25 kHz f = 25 kHz-50 kHz Spurious out-of-band Signals at the Channel Output 0 dBm0, 300 Hz-3400 Hz input PCM applied at DR 4600 Hz-7600 Hz 7600 Hz-8400 Hz 8400 Hz-100,000 Hz 40 40
40 40 40 36
dBp dBc dB dB
NPSRR
40 40 40 36
dBp dBc dB dB
SOS
-32 -40 -32
dB dB dB
12/18
ETC5064 - ETC5064-X - ETC5067 - ETC5067-X
TRANSMISSION CHARACTERISTICS (continued). DISTORTION
Symbol STDX or STDR Parameter Signal to Total Distortion (sinusoidal test method) Transmit or Receive Half-channel Level = 3.0 dBm0 = 0 dBm0 to - 30 dBm0 = - 40 dBm0 = - 55 dBm0 SFDX SFDR IMD Single Frequency Distortion, Transmit (TA = 25C) Single Frequency Distortion, Receive (TA = 25C) Intermodulation Distortion Loop Around Measurement, VFXI + = - 4 dBm0 to - 21 dBm0, two Frequencies in the Range 300 Hz-3400 Hz dBp (ALAW) dBc (LAW) Min. Typ. Max. Unit
XMT RCV XMT RCV
33 36 29 30 14 15 - 46 - 46 - 41
dB dB dB
CROSSTALK
Symbol CTX-R Parameter Transmit to Receive Crosstalk, 0dBm0 Transmit f = 300 Hz-3400 Hz, DR = Steady PCM Code ETC5064/67 ETC5064-X/67-X Receive to Transmit Crosstalk, 0dBm0 Receive Level (note 2) ETC5064/67 f = 300 Hz-3400 Hz, VFXI = 0 V ETC5064-X/67-X Min. Typ. - 90 Max. - 75 - 65 - 70 - 65 Unit dB dB dB dB
CTR-X
- 90
POWER AMPLIFIERS
Symbol VOL Parameter Maximum 0 dBm0 Level for Better than 0.1 dB Linearity Over the Range 10 dBm0 to + 3 dBm0 (balanced load, RL connected between VPO + and VPO -) RL = 600 RL = 1200 RL = 30 k Signal/Distortion RL = 600 , 0 dBm0 Min. Typ. Max. Unit Vrms
33 3.5 4.0 50 dB
S/DP
Notes :
1. Measured by extrapolation from the distortion test results. 2. PPSRX, NPSRX, CTR-X measured with a -50dBm0 activating signal applied at VFXI+
ENCODING FORMAT AT DX OUTPUT
A-Law (Including even bit inversion) VIN (at GSX) = + Full-scale VIN (at GSX) = 0 V VIN (at GSX) = - Full-scale 10101010 11010101 01010101 00101010 Law 10000000 11111111 01111111 00000000
13/18
ETC5064 - ETC5064-X - ETC5067 - ETC5067-X
APPLICATION INFORMATION POWER SUPPLIES While the pins at the ETC506X family are well protected against electrical misure, it is recommended that the standard CMOS practice be followed, ensuring that ground is connected to the device before any other connections are made. In applications where the printed circuit board may be plugged into a "hot" socket with power and clocks already present, an extra long ground pin in the connector should be used. All ground connections to each device should meet at a common point as close as possible to the GNDA pin. This minimizes the interaction of ground return currents flowing through a common bus impedance. 0.1F supply decoupling capacitors should be connected from this common ground point to VCC and VBB as close to the device as possible. For best performance, the ground point of each CODEC/FILTER on a card should be connected to a common card groundin star formation, rather than via a ground bus. This common ground point should be decoupled to VCC and VBB with 10F capacitors. For best performance, TSx should be grounded if not used. Figure 4 : Typical Asynchronous Application.
14/18
ETC5064 - ETC5064-X - ETC5067 - ETC5067-X
SO20 PACKAGE MECHANICAL DATA
DIM. MIN. A a1 a2 b b1 C c1 D E e e3 F L M S 7.4 0.5 12.6 10 1.27 11.43 7.6 1.27 0.75 8 (max.) 0.291 0.020 13.0 10.65 0.35 0.23 0.5 45 (typ.) 0.496 0.394 0.050 0.450 0.300 0.050 0.030 0.510 0.419 0.1 mm TYP. MAX. 2.65 0.2 2.45 0.49 0.32 0.014 0.009 0.020 0.004 MIN. inch TYP. MAX. 0.104 0.008 0.096 0.019 0.013
15/18
ETC5064 - ETC5064-X - ETC5067 - ETC5067-X
PLCC20 PACKAGE MECHANICAL DATA
DIM. MIN. A B D d1 d2 E e e3 F G M M1 1.27 1.14 7.37 1.27 5.08 0.38 0.101 0.050 0.045 9.78 8.89 4.2 2.54 0.56 8.38 0.290 0.050 0.200 0.015 0.004 mm TYP. MAX. 10.03 9.04 4.57 MIN. 0.385 0.350 0.165 0.100 0.022 0.330 inch TYP. MAX. 0.395 0.356 0.180
16/18
ETC5064 - ETC5064-X - ETC5067 - ETC5067-X
DIP20 PACKAGE MECHANICAL DATA
DIM. MIN. a1 B b b1 D E e e3 F I L Z 3.3 1.34 8.5 2.54 22.86 7.1 3.93 0.130 0.053 0.254 1.39 0.45 0.25 25.4 0.335 0.100 0.900 0.280 0.155 1.65 mm TYP. MAX. MIN. 0.010 0.055 0.018 0.010 1.000 0.065 inch TYP. MAX.
17/18
ETC5064 - ETC5064-X - ETC5067 - ETC5067-X
Information furnished is believed to be accurate and reliable. However, SGS-THOMSON Microelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of SGS-THOMSON Microelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. SGS-THOMSON Microelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of SGS-THOMSON Microelectronics. (c) 1994 SGS-THOMSON Microelectronics - All Rights Reserved SGS-THOMSON Microelectronics GROUP OF COMPANIES Australia - Brazil - France - Germany - Hong Kong - Italy - Japan - Korea - Malaysia - Malta - Morocco - The Netherlands - Singapore Spain - Sweden - Switzerland - Taiwan - Thaliand - United Kingdom - U.S.A.
18/18

▲Up To Search▲

Price & Availability of ETC5067

	To Download ETC5067 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .